1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Related Art
In some cases, an interlayer dielectric, such as a via dielectric having a via wiring provided therein or a trench dielectric having a trench wiring provided therein, requires a low dielectric constant (Low-k). There is a semiconductor device in which an interlayer dielectric is a porous layer in order to reduce dielectric constant.
However, in this case, the mechanical strength of the interlayer dielectric is reduced. For example, when chemical mechanical polishing (CMP) is performed after a metal material is buried, a layer structure is likely to be destroyed. In addition, in some cases, the adhesion between the interlayer dielectric and a layer coming into contact with the interlayer dielectric is reduced and the dielectric is likely to peel off.
As a means for solving the above-mentioned problems, for example, there is a technique disclosed in Japanese Unexamined Patent Publication No. 2005-117026. In the technique disclosed in Japanese Unexamined Patent Publication No. 2005-117026, the process (for example, the application of a solution and drying) that has been performed once in order to form a porous layer is performed two or more times. In this way, it is possible to appropriately distribute pores in the porous layer. As a result, it is possible to prevent the porous layer from peeling off.
In the technique disclosed in Japanese Unexamined Patent Publication No. 2005-117026, it is difficult to sufficiently improve the mechanical strength of the interlayer dielectric.
The inventors conducted a study on a technique capable of reducing the dielectric constant of an interlayer dielectric and improving the mechanical strength of the interlayer dielectric. As a result, the inventors found the following problems.
(1) Raw Material
In general, in the case of a raw material (for example, a silsesquioxane resin (SiOC)) used for a low-dielectric constant (low-k) porous layer, the network of “—Si—O—Si—” is terminated by C. As a result, the mechanical strength of the layer is reduced. When C is incorporated into the network, for example, “—O—Si—C—Si—” is formed. As a result, the raw material is close to “SiC”, which is a semiconductor, and leakage current increases.
(2) Difference in Structure Between Via Dielectric and Trench Dielectric
In general, each of the via dielectric and the trench dielectric includes an interlayer dielectric and a metal layer. The occupancy of the interlayer dielectric in the via dielectric is larger than that of the interlayer dielectric in the trench dielectric. For example, in some cases, the volume ratio of the interlayer dielectric in the via dielectric is 10 to 1000 times larger than the volume ratio of the interlayer dielectric in the trench dielectric. Mechanical strength to destroy each layer is determined by, for example, the mechanical strength of each of the interlayer dielectric, the trench wiring, and the via wiring, the volume ratio of each layer, and the adhesion strength between the interlayer dielectric and the trench wiring or the via wiring. In many cases, destruction occurs in the interlayer dielectric whose mechanical strength is about a fraction of the mechanical strength of the trench wiring and the via wiring. Therefore, the via dielectric in which the occupancy of the interlayer dielectric is needs to have higher mechanical strength. However, when the via dielectric and the trench dielectric are designed in the same way without considering the above, the flexibility of the design is reduced and it is difficult to obtain sufficient dielectric constant and mechanical strength.
The inventors achieved the invention considering the above-mentioned problems.